The present invention relates to integrated circuit chip packages, and in particular to a moisture-resistant integrated circuit chip package and method.
In some ball grid array (BGA) packages, a substrate is provided with vias. A conductor such as copper is patterned on both sides of the substrate and fills the vias. The copper in the vias provides an electrical connection between conductive areas the top side (xe2x80x9cchip sidexe2x80x9d) of the substrate and conductive areas on the bottom side (xe2x80x9cball sidexe2x80x9d) of the substrate. A plating material such as nickel-gold is typically used as the etch mask when the copper is patterned. This means that nickel-gold plate is present not only in the bond pad and solder pad areas of the copper, but also wherever a trace is present on either side of the substrate. A soldermask formed to cover both sides of the substrate while leaving bond pad and solder pad areas uncovered. This means that the soldermask material covers the nickel-gold plating over the conductive traces. Conventional soldermask material does not adhere well to nickel-gold. This lack of adhesion results in poor moisture resistance. For example, JEDEC Level 2 Moisture Resistance Testing exposes a package to 60% relative humidity at 85xc2x0 C. for 192 hours. BGA packages manufactured using the above-described conventional process cannot meet this level of moisture resistance testing.
Therefore, a need has arisen for an integrated circuit chip package that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for an integrated circuit chip package with high moisture resistance.
Accordingly, an integrated circuit chip package is disclosed. In one embodiment, the integrated circuit chip package includes a substrate having a chip side and a backside. A first conductive layer is formed on the chip side of the substrate, and has a pattern forming conductive traces. A first soldermask layer is formed on the chip side of the substrate. The first soldermask layer directly contacts the first conductive layer. The first soldermask layer has at least one opening formed therein. A first contact layer is formed over the first conductive layer in the opening of the first soldermask layer. A second conductive layer is formed on the backside of the substrate. A second soldermask layer is formed on the back side of the substrate and has at least one opening formed therein. A second contact layer overlies the second conductive layer in the opening of the second soldermask layer.
In another aspect of the present invention, a method for fabricating an integrated circuit chip package is disclosed. In one embodiment, the method includes forming a first conductive layer on a first side of a substrate, forming a second conductive layer on a second side of the substrate, forming an electrical connection between the first and second conductive layers, selectively etching the first conductive layer to form a first pattern on the first side of the substrate, forming a soldermask layer over selected portions of the first side of the substrate, electroplating a first contact layer on at least one portion of the first conductive layer exposed by the soldermask layer to form at least one contact area, and electroplating a second contact layer on the second conductive layer.
An advantage of the present invention is that the soldermask layer on the chip side of the substrate has high adhesion to the conductive layer. This results in a higher level of moisture resistance for the package.